This invention relates to a static type RAM (random access memory) comprising MOSFETs (insulated gate field effect transistors), and to a technique which is effective when applied to a RAM constituted by a CMOS (complementary MOS) circuit, for example.
A memory cell in an MOS static type RAM is comprised, for example, of a static type flip-flop circuit comprising a pair of driving MOSFETs whose gates and drains are mutually cross-coupled and its load element, and a pair of transfer gate MOSFETs. A memory array includes a plurality of such memory cells arranged in a matrix and a plurality of complementary data line pairs to which input-output terminals of the corresponding memory cells are respectively connected. A load element comprising, for example, an MOSFET which is continuously turned on, is interposed between each complementary data line and the power terminal of the circuit. (For a RAM having a structure in which the load resistors are connected to the data lines, refer to U.S. patent specification No. 4,272,834, for example.)
The load resistors connected to the complementary data lines operate in such a fashion as to set the potential of the complementary data lines to a predetermined potential before a data read-out operation from the memory cells and before a data write-in operation into them. The access time of the memory in the data read-out and write-in operations can be made constant by the previous setting of the potential of the complementary data lines.
As a result of studies, however, the inventors of the present invention have found that the following problems occur when fixed resistance loads constituted by MOSFETs described above are used.
In the data read-out operation, a predetermined word line is selected, thereby selecting a certain memory cell. Then, the level of a pair of complementary data lines is determined by the selected memory cell. In this case, the read-out low level of one of the complementary data lines is determined by the conductance ratio of the conductance characteristics of the driving MOSFETs and transfer gate MOSFETs to the conductance characteristics of the load MOSFETs. When a plurality of memory cells are sequentially selected in order to continuously read out the data (stored information) stored in a plurality of memory cells, the levels of the complementary data lines are sequentially determined by the selected memory cells. In this case, if data of the opposite level is read out such as when the stored information of a logic "1" is read out after the read-out of the stored information of a logic "0", for example, the levels of the complementary data lines are changed by a large amount from the high and low levels to the low and high levels, respectively. Here, the level changing speed of each complementary data line is limited by unnegligible capacitance which comprises a parasitic capacitance and a stray capacitance coupled to the complementary data lines. As a result, the data read-out speed is restricted.
The inventors of the present invention pay specific attention to the fact that when the level change width of each of the complementary data lines is reduced, the time of the change, from one level to the other can be reduced, that the charge-up speed to the complementary data lines can be increased by increasing the conductance of the load MOSFETs ahd the level change width of the complementary data lines can be reduced, as well. Therefore, the inventors have examined the possibility of increasing as much as possible the conductance of the load MOSFETs in order to realize a high speed read-out operation.
It has been found, however, that the following new problem develops. That is, the read-out operation is substantially effected for a memory cell which is coupled to the unselected complementary data lines in the write-in operation and which is selected by the word line. Therefore, if the conductance of the load MOSFETs are increased, a relatively great current flows between the load MOSFETs and the selected memory cells. A current flowing between the memory cell coupled to the unselected complementary data line and the load MOSFET is irrelevant to the write-in data; hence, it is essentially a wasteful current. However, the read-out speed will be reduced if the conductance characteristics of the load MOSFETs, are reduced in order to reduce this wastefull current.